The present invention generally concerns control of equivalent series inductance (ESL) of decoupling capacitors, and more particularly, concerns low inductance terminations for a grid array capacitor. The subject invention concerns a capacitor array that can be utilized in either ball grid array or land grid array configurations and that provides a lower ESL and thus a much more efficient capacitor device.
Integrated circuits (ICs) have been implemented for some time, but many specific features of these ICs affect the design criteria for electronic components and corresponding procedures for mounting such components. With increased functionality of integrated circuit components, the design of electronic components must become increasingly more efficient. The miniaturization of electronic components is a continuing trend in the electronics industry, and it is of particular importance to design parts that are sufficiently small, yet simultaneously characterized by high operating quality. Components are desired that are small in size and that have reliable performance characteristics, yet can be manufactured at relatively low costs.
Component miniaturization enables higher density mounting on circuit boards or other foundations. Thus the spacing between components is also a limiting factor in present integrated circuit designs. Since spacing is such a critical design characteristic, the size and location of termination means or elements for IC components is also a significant design characteristic.
One specific electronic component that has been used in IC applications is the decoupling capacitor. Decoupling capacitors are often used to manage noise problems that occur in circuit applications. They provide stable, local charge sources required to switch and refresh the logic gates used in present digital circuits. A dramatic increase in the speed and packing density of integrated circuits requires advancements in decoupling capacitor technology. When high-capacitance decoupling capacitors are subjected to the high frequencies of many present applications, performance characteristics become increasingly more important. One way to achieve improved performance is by lowering the inductance of the device. Thus, it is ideal that such capacitive structures provide low equivalent series inductance (ESL) in order to maintain circuit efficiency.
Several design aspects have been implemented that reduce the self and mutual inductance of decoupling capacitors. Reducing the current path will lower self inductance. Since the current often has to travel the entire length of the capacitor, termination on the longer ends of the structure will reduce the current path. If the current in adjacent capacitor electrodes flows in opposite directions it will reduce the mutual inductance in a capacitor. Multiple terminations as utilized in interdigitated capacitor technology lowers the inductance value.
Another approach to lowering the ESL of a decoupling capacitor is to minimize interconnect induction that results from termination configurations and mounting systems. Typical termination schemes incorporate long traces to the capacitor electrode pads. Such a connection is characterized by high inductance and often prohibits very close spacing between components. Thus, a more efficient termination is desired that has low ESL and that facilitates high component density for integrated circuits. It is also ideal to provide such an efficient termination scheme without decreasing the volumetric efficiency of the component.
Yet another contribution to lowering the ESL of a decoupling capacitor lies in reducing the current path between a ground plane or power plane in an integrated circuit to the electrode plates in a multilayer capacitor configuration. Typical multilayer capacitor designs require relatively thick cover layers on both top and bottom of such a multilayer configuration. These protective layers ideally provide sufficient bulk to withstand the stress of typical glass/metal frit that must be fired to a capacitor body. This typical need for protective outer layers hinders potential reduction of loop inductance.
In the context of decoupling capacitors, it is often ideal to incorporate other design characteristics based on specific applications. Customers of capacitor manufacturers often specify such choices, including capacitor packaging configuration and termination composition. In particular, it is convenient to have capacitors that can encompass either land grid array or ball grid array designs. It is ideal to incorporate such options into a capacitor design in a cost-effective and convenient manner.
While examples of various aspects and alternative embodiments are known in the field of multilayer decoupling capacitors, no one design is known that generally encompasses all of the above-referenced preferred capacitor characteristics.
U.S. Pat. No. 6,064,108 shows an example of a multilayer capacitor that incorporates an arrangement of xe2x80x9cinterdigitatedxe2x80x9d capacitor plates. Such ""108 patent represents an exemplary electrode configuration that enables reliable high-capacitance multilayer devices.
U.S. Pat. No. 5,661,450 discloses resistor arrays with low inductance termination schemes. Such arrays include conductive vias through a substrate with attached solder balls. This configuration is exemplary of a design that achieves low inductance connections for an integrated circuit environment.
U.S. Pat. Nos. 5,666,272 and 5,892,245 disclose examples of ball grid array (BGA) packages that facilitate increased component density on circuit boards.
U.S. Pat. No. 6,097,609 shows an exemplary packaging assembly that is compatible with both ball grid array (BGA) and land grid array (LGA) design configurations.
U.S. Pat. No. 5,880,925 discloses an exemplary multilayer capacitor with an interdigitated arrangement of lead structures.
Japanese Pat. Nos. 1-37756 and 7-37775 reference capacitor arrays capable of high density component packaging.
Additional patents provide varied examples of capacitor designs, as follows.
The disclosures of all of the foregoing United States patents are hereby fully incorporated into this application by reference thereto.
In view of the discussed drawbacks and other shortcomings encountered in the prior art, and recognized and addressed by the present invention, improved low inductance capacitor technology has been developed. Thus, broadly speaking, a general object of the present invention is improved termination schemes for multilayer capacitor arrays.
It is another general object of the present invention to provide a low inductance capacitor array that facilitates closer component spacing in an integrated circuit environment.
It is a principal object of the present invention to provide capacitor array technology that is compatible with both ball grid array and land grid array packaging configurations.
It is another principal object of the present invention to provide a multilayer capacitor array with lowered equivalent series inductance (ESL).
It is another object of the present invention to provide capacitors with interdigitated electrode configurations that may define a single capacitor or a capacitor array.
It is a further object of the present invention to provide improved termination schemes for multilayer capacitor arrays without significant decrease in the volumetric efficiency of such capacitor arrays.
Additional objects and advantages of the invention are set forth in, or will be apparent to those of ordinary skill in the art from, the detailed description herein. Also, it should be further appreciated that modifications and variations to the specifically illustrated, referenced and discussed features hereof may be practiced in various embodiments and uses of this invention without departing from the spirit and scope thereof, by virtue of present reference thereto. Such variations may include, but are not limited to, substitution of equivalent means and features for those illustrated, referenced or discussed, and the functional, operational or positional reversal of various parts, features or the like.
Still further, it is to be understood that different embodiments, as well as different presently preferred embodiments, of this invention may include various combinations or configurations of presently disclosed features or elements, or their equivalents (including combinations of features or parts or configurations thereof not expressly shown in the figures or stated in the detailed description). One exemplary such embodiment of the present subject matter relates to a multilayer capacitor. Such capacitive element may comprise a body of dielectric material, a plurality of electrode layers and electrode tabs, a plurality of vias and a conductive material for termination formation.
More preferably, such exemplary dielectric layers and electrode layers are interleaved to form a multilayer configuration. Electrode tabs may extend from certain electrode layers in a predefined manner such that vias are formed through a combination of selected electrode tabs. A conductive material may then preferably fill the conductive vias to form multiple capacitor terminations.
Another present exemplary embodiment of the present subject matter concerns such a multilayer capacitor as described above for use as a capacitor array. Such capacitor array may preferably be configured for use with either ball grid array (BGA) or land grid array (LGA) packaging techniques. More preferably, such an array configuration may comprise a multilayer arrangement of dielectric and electrode layers, electrode tabs extending from selected electrode layers, and conductive vias defined through predefined electrode tabs. The vias may then be preferably filled with a conductive material, forming a columnar termination to which solder balls may be attached.
Still further exemplary embodiments of the present subject matter involve various combinations of selected of the foregoing features, wherein selected of the exemplary electrode layers are subdivided to provide multiple discrete capacitive elements. This optional feature in the disclosed embodiments facilitates the versatile design choice to create either a single multilayer capacitor or a multilayer capacitor array.
Additional embodiments of the subject invention, not necessarily expressed in this summarized section, may include and incorporate various combinations of aspects of features or parts referenced in the summarized objectives above, and/or other features, parts, or elements as otherwise discussed in this application.
Those of ordinary skill in the art will better appreciate the features and aspects of such embodiments, and others, upon review of the remainder of the specification.